The Execution Cycle Simulation - part II
  
 
address bus
data bus
control bus
   

  Read Only Memory (ROM)
CPU
 
PC
0000
IR
EB
MAR
61F8
A
36
 
49C9
 
E2
 
  0 1 2 3 4 5 6 7 8 9 A B C D E F
0000 3E 05 E4 E4 E5 D6 00 00 FF FF FF FF FF FF FF FF
0010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0020 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0030 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

 

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