The Execution Cycle Simulation - part III
  
 
address bus
data bus
control bus
   

  Read Only Memory (ROM)
CPU
 
PC
0130
IR
C3
MAR
9CAD
A
EF
 
1292
 
A4
 
  0 1 2 3 4 5 6 7 8 9 A B C D E F
00F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0100 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0110 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0120 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0130 3E 03 E5 D7 30 01 D6 32 01 FF FF FF FF FF FF FF
0140 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0150 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0160 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

 

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